ADC Flags Register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers).
| THCMP0 | Threshold comparison event on Channel 0. Set to 1 upon either an out-of-range result or a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by writing a 1. |
| THCMP1 | Threshold comparison event on Channel 1. See description for channel 0. |
| THCMP2 | Threshold comparison event on Channel 2. See description for channel 0. |
| THCMP3 | Threshold comparison event on Channel 3. See description for channel 0. |
| THCMP4 | Threshold comparison event on Channel 4. See description for channel 0. |
| THCMP5 | Threshold comparison event on Channel 5. See description for channel 0. |
| THCMP6 | Threshold comparison event on Channel 6. See description for channel 0. |
| THCMP7 | Threshold comparison event on Channel 7. See description for channel 0. |
| THCMP8 | Threshold comparison event on Channel 8. See description for channel 0. |
| THCMP9 | Threshold comparison event on Channel 9. See description for channel 0. |
| THCMP10 | Threshold comparison event on Channel 10. See description for channel 0. |
| THCMP11 | Threshold comparison event on Channel 11. See description for channel 0. |
| OVERRUN0 | Mirrors the OVERRRUN status flag from the result register for ADC channel 0 |
| OVERRUN1 | Mirrors the OVERRRUN status flag from the result register for ADC channel 1 |
| OVERRUN2 | Mirrors the OVERRRUN status flag from the result register for ADC channel 2 |
| OVERRUN3 | Mirrors the OVERRRUN status flag from the result register for ADC channel 3 |
| OVERRUN4 | Mirrors the OVERRRUN status flag from the result register for ADC channel 4 |
| OVERRUN5 | Mirrors the OVERRRUN status flag from the result register for ADC channel 5 |
| OVERRUN6 | Mirrors the OVERRRUN status flag from the result register for ADC channel 6 |
| OVERRUN7 | Mirrors the OVERRRUN status flag from the result register for ADC channel 7 |
| OVERRUN8 | Mirrors the OVERRRUN status flag from the result register for ADC channel 8 |
| OVERRUN9 | Mirrors the OVERRRUN status flag from the result register for ADC channel 9 |
| OVERRUN10 | Mirrors the OVERRRUN status flag from the result register for ADC channel 10 |
| OVERRUN11 | Mirrors the OVERRRUN status flag from the result register for ADC channel 11 |
| SEQA_OVR | Mirrors the global OVERRUN status flag in the SEQA_GDAT register |
| SEQB_OVR | Mirrors the global OVERRUN status flag in the SEQB_GDAT register |
| RESERVED | Reserved. |
| SEQA_INT | Sequence A interrupt/DMA trigger. If the MODE bit in the SEQA_CTRL register is 0, this flag will mirror the DATAVALID bit in the sequence A global data register (SEQA_GDAT), which is set at the end of every ADC conversion performed as part of sequence A. It will be cleared automatically when the SEQA_GDAT register is read. If the MODE bit in the SEQA_CTRL register is 1, this flag will be set upon completion of an entire A sequence. In this case it must be cleared by writing a 1 to this SEQA_INT bit. This interrupt must be enabled in the INTEN register. |
| SEQB_INT | Sequence A interrupt/DMA trigger. If the MODE bit in the SEQB_CTRL register is 0, this flag will mirror the DATAVALID bit in the sequence A global data register (SEQB_GDAT), which is set at the end of every ADC conversion performed as part of sequence B. It will be cleared automatically when the SEQB_GDAT register is read. If the MODE bit in the SEQB_CTRL register is 1, this flag will be set upon completion of an entire B sequence. In this case it must be cleared by writing a 1 to this SEQB_INT bit. This interrupt must be enabled in the INTEN register. |
| THCMP_INT | Threshold Comparison Interrupt. This bit will be set if any of the THCMP flags in the lower bits of this register are set to 1 (due to an enabled out-of-range or threshold-crossing event on any channel). Each type of threshold comparison interrupt on each channel must be individually enabled in the INTEN register to cause this interrupt. This bit will be cleared when all of the individual threshold flags are cleared via writing 1s to those bits. |
| OVR_INT | Overrun Interrupt flag. Any overrun bit in any of the individual channel data registers will cause this interrupt. In addition, if the MODE bit in either of the SEQn_CTRL registers is 0 then the OVERRUN bit in the corresponding SEQn_GDAT register will also cause this interrupt. This interrupt must be enabled in the INTEN register. This bit will be cleared when all of the individual overrun bits have been cleared via reading the corresponding data registers. |